1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including an inductor and a fabrication method thereof.
2. Description of the Related Art
FIG. 1 is a plan view of a conventional semiconductor integrated circuit, and FIG. 2 is a cross-sectional view thereof, taken along the line E-E in FIG. 1. As shown in FIGS. 1 and 2, in this conventional semiconductor integrated circuit, a multilayer interconnection layer 101 is provided on a semiconductor substrate (not shown). In the uppermost layer 102 of the multilayer interconnection layer 101, an inductor 103 is provided. The inductor 103 is a spiral inductor. In other words, on an insulating layer 104 formed of SiO2 in the multilayer interconnection layer 101, the inductor 103 is provided. The inductor 103 is formed by a single wiring that is spirally arranged. In addition, an insulating layer 105 formed of SiO2 is provided to cover the inductor 103. An insulating layer 106 formed of polyimide is provided on the insulating layer 105. In FIG. 1, the insulating layers 105 and 106 are not shown.
The wiring constituting the inductor 103 is formed by covering an upper surface and a lower surface of a wiring body layer 107 formed of copper or aluminum with TiW layers 108. The reason why the inductor 103 is provided in the uppermost layer 102 of the multilayer interconnection layer 101 is to make a parasitic capacitance between the inductor 103 and the semiconductor substrate as small as possible and to make the thickness of the wiring of the inductor 103 as thick as possible so as to reduce a series resistance, thereby improving a Q value of the inductor 103.
However, this conventional semiconductor integrated circuit has the following problem. Even in the case where the inductor 103 is arranged in the uppermost layer 102 of the multilayer interconnection layer 101, the upper limit of the thickness of the inductor 103 is several microns because the thickness of the uppermost layer 102 is about 10 μm at a maximum. Thus, loss of inductance is large and the Q value is as low as about 5 to about 10. Moreover, in order to obtain inductance of 10 nH, for example, the inductor 103 should be formed in the shape of a square spiral having a side of 200 to 300 μm. That is, an area occupied by the inductor 103 is very large. This prevents miniaturization of the semiconductor integrated circuit.
Thus, Japanese Utility-Model Laid-Open Publication No. Hei 3-28758 discloses a technique for providing the ferromagnetic layer in a layer upper than the inductor. According to this technique, the ferromagnetic layer is provided directly above a region corresponding to the inside of the spiral formed by the wiring of the inductor. In addition, Japanese Utility-Model Laid-Open Publication No. Hei 4-63653 discloses a technique for providing the ferromagnetic layer above or below the inductor. According to this technique, the ferromagnetic layer is provided to cover the inductor, when seen from a direction perpendicular to a surface of a substrate. Furthermore, Japanese Patent Laid-Open Publication No. Sho 61-161747 discloses a technique for providing the ferromagnetic layer above the inductor. This publication describes that provision of the ferromagnetic layer increases inductance of the inductor.
However, the aforementioned conventional techniques have the following problem. In each of the semiconductor integrated circuits described in Japanese Utility-Model Laid-Open Publications Nos. Hei 3-28758 and Hei 4-63653 and Japanese Patent Laid-Open Publication No. Sho 61-161747, the inductance and the Q value of the inductor are not sufficient. In order to obtain a predetermined magnitude of inductance, each semiconductor integrated circuit requires an inductor having a larger area. Thus, it is not-possible to sufficiently miniaturize the semiconductor integrated circuit.